The present invention relates to a buffer circuit, and, in particular, to a buffer circuit which is suitable for driving a high capacitance load or a high current load.
As a buffer circuit capable of driving a comparatively heavy load, a TTL (transistor-transistor logic) circuit is well known. The circuit of FIG. 1 includes NPN transistors 11, 12 and 13 respectively having Schottky clamps, a level shift diode 14, and resistors 15, 16 and 17.
When the voltage V.sub.I at an input terminal 10 is switched to the high level, NPN transistors 11 and 13 turn ON to turn an NPN transistor 12 OFF. Accordingly, the charge stored in a load C.sub.L is discharged to the ground potential GND through the NPN transistor 13. Thus, the potential V.sub.O at an output terminal 18 is switched to its low level. When the potential V.sub.I at the input terminal 10 is switched to its low level, the NPN transistors 11 and 13 turn OFF to turn the NPN transistor 12 ON. Thus, a current from a power supply terminal 19 flows to a load c.sub.L to charge it through the resistor 17, the NPN transistor 12, and the diode 14. Thereby, the potential V.sub.O at the output terminal 18 changes to its high level. The circuit illustrated in FIG. 1 is advantageous in that it is capable of switching a heavy load at high speed. For preventing the NPN transistors 11, 12 and 13 from being saturated, however, Schottky diodes must be formed, resulting in a high production cost.
An output buffer circuit such as a TTL circuit having an output stage comprising a bipolar transistor must be capable of sinking a predetermined DC current I.sub.O at a predetermined output voltage V.sub.OL when the output is at its low level. For example, in a typical TTL circuit, V.sub.OL =0.4 V and I.sub.OL =16 mA. When the voltage V.sub.I at the input terminal 10 assumes its high level, therefore, a current from the power supply terminal 19 must always flow to the base of the NPN transistor 13 through the resistor 15 and the NPN transistor 11 so that I.sub.OL (=16 mA) may flow through the NPN transistor 13. This results in large power dissipation.
Further, the bipolar transistor used in the output stage has a charge storage effect. Therefore, the charge stored in the base of the bipolar transistor prolongs the time required for the bipolar transistor to turn OFF.
As another conventional buffer circuit capable of driving a comparatively heavy load, a CMOS (complementary metal-oxide-semiconductor) circuit as illustrated in FIG. 2 is widely known. In FIG. 2, reference numerals 21 and 23 denote PMOS (P-channel metal-oxide-semiconductor or P-channel insulated gate field-effect) transistors, and reference numerals 22 and 24 denote NMOS (N-channel metal-oxide-semiconductor or N-channel insulated gate field-effect) transistors. The PMOS 21 and NMOS 22 constitute a driver-stage inverter. The PMOS 23 and NMOS 24 constitute an output-stage inverter.
When the potential V.sub.I at an input terminal 20 is switched to its high level, the PMOS 21 turns OFF and the NMOS 24 turns OFF. Subsequently, the PMOS 23 turns ON and the NMOS 24 turns OFF. Accordingly, a charging current from the power supply terminal 26 feeding the voltage V.sub.CC flows to a load C.sub.L through the PMOS 23. Thus, the potential V.sub.O at an output terminal 25 is switched to its high level. When the voltage V.sub.I at the input terminal 20 is switched to its low level, the PMOS 21 turns ON and the NMOS 22 turns OFF. Subsequently, the PMOS 23 turns OFF and the NMOS 24 turns ON. Accordingly, the charge stored in the load C.sub.L is discharged to the ground potential GND through the NMOS 24. Thus, the potential V.sub.O at the output terminal 25 assumes its low level.
In the steady states wherein the input potential V.sub.I assumes its high level or its low level, the dissipated power in the FIG. 2 arrangement is nearly zero. Thus, the most significant advantage of the circuit illustrated in FIG. 2 is its low power dissipation. However, it is difficult to attain high speed operation. And the dissipated power of the circuit during switching depends upon the rising and falling characteristics of the switching waveform at the driver stage and tends to become large.
For enhancing the load drive capability of the output stage in the circuit of FIG. 2, the channel width W of the PMOS 23 and NMOS 24 located at the output stage must be designed to be large. FIG. 3 shows plots of delay time as functions of the load capacity. In FIG. 3, it is assumed that each of the PMOS 21 and NMOS 22 of the driver stage illustrated in FIG. 2 has a channel width W.sub.1 and the channel width of each of the PMOS 23 and NMOS 24 located at the output stage is W.sub.1 or 2W.sub.1. Even if the driving capability of the output stage is doubled, the delay time is increased for a load capacitance below C.sub.1 as illustrated in FIG. 3. Since the channel width of the PMOS 23 and the NMOS 24 located at the output stage has been doubled, the gate input capacitance is also doubled. Because of the resultant insufficient capability of the driver stage, the delay time has been prolonged as illustrated in FIG. 3.
Because of insufficient driving capability of the driver stage, another problem is also caused. The input waveform of the output stage varies more slowly because of the insufficient drive capability of the driver stage. During switching transition of the output stage, therefore, the time duration during which both the PMOS 23 and NMOS 24 remain in the ON state is prolonged. As a result, the power dissipation during the switching operation increases as illustrated in FIG. 4. When the rise time t.sub.r and the fall time t.sub.f in the driving waveform of the output stage are 15 ns, the dissipated power is increased by nearly 20% as compared with that when t.sub.r and t.sub.f are 1 ns.
From the above described reasons, in the CMOS circuit comprising a minimum number of stages, i.e., the driver stage and the output stage, the driving capability of the driver stage limits an increase in the operation speed. Unless the balance between the drive capability of the driver stage and that of the output stage is optimized in design, the power dissipation is increased. This problem holds true to not only CMOS circuits but also NMOS circuits and PMOS circuits. For a MOS circuit which must have high load driving capability, therefore, a multi-stage driver circuit is used and the MOS channel width is increased as the stage approaches the output stage.
A design method for this multi-stage driver circuit is disclosed in U.S. Pat. 4,016,431, for example. FIG. 5 is quoted from the U.S. Patent. Between a signal driver stage 41 and an output stage 42 illustrated in FIG. 5, N-intermediate driver stages 43 and 44 are placed. The total delay time of such a multi-stage driver circuit is minimized when the number N of intermediate stages and the capacitance Ci of an intermediate stage respectively satisfy ##EQU1## where Cd=load capacitance of the output stage,
Cl=load capacitance of the signal driver stage, PA1 C.sub.i-1 =capacitance of the preceding stage, PA1 C.sub.i+1 =capacitance of the succeeding stage.
If Cd=100 pF and Cl=0.1 pF, for example, the number N of intermediate stages is 6, and 7 stages including the output stage are required. If the load drive capability of a conventional multi-stage driver circuit is increased, therefore, the number of stages is also increased, resulting in the increased power dissipation. Since the total delay time is also increased due to the number of increased stages, it was difficult to raise the operation speed.